1. Field of the Invention
The present invention relates to an input circuit. In particular, the present invention relates to an input circuit having an offset voltage adjustment circuit.
2. Description of Related Art
In recent years, semiconductor apparatuses have been required to have a smaller size and reduced power consumption due to an electric signal having a higher speed used in an electronic device and a larger circuit size of the entire semiconductor apparatus used in an electronic device. In accordance with this, reducing the power consumption of a basic circuit configuration of a semiconductor apparatus has been important. In particular, reducing the power consumption of an input circuit including a buffer circuit for handling an analog input signal has been important because such an input circuit is a continuous time processing system.
Such an input circuit is generally inserted between a precedent stage circuit such as an analog input signal source and a subsequent stage circuit such as an analog/digital converter. Such an input circuit has a function to adjust the impedance and offset voltage for the precedent stage circuit and the subsequent stage circuit.
FIG. 1 illustrates a related input circuit. With reference to FIG. 1, an impedance adjustment function will be described. An analog input signal from an input signal terminal 1 is received in a buffer circuit 120. The buffer circuit 120 outputs an output signal to an output signal terminal 5. The input impedance of the buffer circuit 120 is designed to be high and the output impedance thereof is designed to be low. Thus, the input impedance for the output of the precedent stage circuit is high and the output impedance for the input of the subsequent stage circuit is low. With this configuration, it can be prevented that current flows between the output of the precedent stage circuit and the input of the subsequent stage circuit to reduce a signal potential. It can be prevented also that sufficient current is not supplied between the output of the precedent stage circuit and the input of the subsequent stage circuit.
Next, with reference to FIG. 1, an offset voltage adjustment function will be described. This function is used to adjust a center voltage of an output signal level of the precedent stage circuit with a center voltage of an input signal of the subsequent stage circuit. With reference to FIG. 1, an intermediate voltage between the voltage VRT at an external reference voltage terminal 65 and the voltage VRB at an external reference voltage terminal 60 is generated by resistance voltage division. The intermediate voltage is output to the input side of the buffer circuit 120 via a differential amplification circuit 140 and the DC bias the resistance 110. As a result, the center voltage of the output signal terminal 5 is adjusted. When the buffer circuit 120 and the replica buffer circuit 130 have the same voltage gain, then the intermediate voltage value is the same as a center voltage value of a signal output to an output terminal 5. The reason is that, when the voltage gain of the replica buffer circuit 130 is assumed as C, then a voltage C times higher than the output of the differential amplification circuit 140 is input to an inverting input terminal of the differential amplification circuit 140 and thus the output voltage of the differential amplification circuit 140 is 1/C of the intermediate voltage. On the other hand, the voltage of a node 118 is increased by the buffer circuit 120 by a factor of C. Thus, the center voltage of the signal at the output terminal 5 is equal to the intermediate voltage.
The technique as described above is also disclosed in U.S. Pat. No. 7,126,377 for example.